"Analysis on Via Design for Impedance Mismatch Minimization in High Speed Channel" by Jaemin Lim

Article

Analysis on Via Design for Impedance Mismatch Minimization in High Speed Channel

Proceedings of the 7th Asia-Pacific International Symposium on Electromagnetic Compatibility & Signal Integrity and Technical Exhibition, APEMC 2016 (2016, Shenzhen, China)

Jaemin Lim
Joungho Kim
DongHyun Kim, Missouri University of Science and Technology
For full list of authors, see publisher's website., For full list of authors, see publisher's website.

Link

Meeting Name

7th Asia-Pacific International Symposium on Electromagnetic Compatibility & Signal Integrity and Technical Exhibition, APEMC 2016 (2016: May 18-21, Shenzhen, China)

Department(s)

Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Publication Date

5-1-2016

Publication Date

01 May 2016

Disciplines

Electromagnetics and Photonics

Citation Information

Jaemin Lim, Joungho Kim, DongHyun Kim and For full list of authors, see publisher's website.. "Analysis on Via Design for Impedance Mismatch Minimization in High Speed Channel" Proceedings of the 7th Asia-Pacific International Symposium on Electromagnetic Compatibility & Signal Integrity and Technical Exhibition, APEMC 2016 (2016, Shenzhen, China) (2016)
Available at: http://works.bepress.com/donghyun-bill-kim/52/