We compare two 16 bit adders based on the Manchester Carry Chain (MCC) circuit topology using the TSMC .25 µm process technology. The first circuit is a synchronous 16 bit adder based on an optimized 4-bit MCC where the carry out of each of the 4-bit MCCs are ripple carried into the next MCC block through an edge sensitive D-Flip Flop. The second circuit is an asynchronous adder, which uses the same optimized four-bit MCC structure as our synchronous design, except the carry out signals are now controlled asynchronously with request acknowledge signals generated with Muller-C elements. The asynchronous design has less average delay and uses less power than the synchronous design at the expense of increased area, and longer design time. We also compare our asynchronous adder design to other 32 bit asynchronous designs by measuring the propagation delay though 5 carries (the average carry length of a 32 bit adder). In order to compare designs that have been designed with different technologies, we attempt to scale the area, delay, and power by using lambda rules and ring oscillator delay and power results available on the MOSIS website. Results show that the MCC based asynchronous adder is approximately two times faster than other adders with approximately the same power dissipation.