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Pixel Level Analog to Digital Converter
Proceedings of the 16’th Bi Annual University, Government, Industry Microelectronics (UGIM) Symposium (2006)
  • Nguyen Phong
  • Joseph Chung
  • Mariavanessa Pascua
  • Scott Tarkul
  • Eric Vasham
  • David W Parent, San Jose State University
Abstract
A semi custom design flow was used to implement and fabricate an analog circuit. The pixel level detector circuit was designed on a sea-of-gates called an analog-leaf-cell. Cadence Tools was used to design the schematic, layout, and simulate the analog circuit. Once the layout and schematic has been verified (LVS) on Cadence tools, a post extraction simulation is observed. When all specifications have been reached, the circuit design is ready to be fabricated and is sent out to MOSIS. Eight weeks later, the integrated circuit is fabricated and packaged into an IC chip and returned to students to be tested.
Publication Date
2006
Publisher Statement
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Citation Information
Nguyen Phong, Joseph Chung, Mariavanessa Pascua, Scott Tarkul, et al.. "Pixel Level Analog to Digital Converter" Proceedings of the 16’th Bi Annual University, Government, Industry Microelectronics (UGIM) Symposium (2006)
Available at: http://works.bepress.com/david_parent/31/