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Article
6 Bit Decimation Filter in Sub-threshold Region
Proceedings of the 16’th Bi Annual University, Government, Industry Microelectronics (UGIM) Symposium (2006)
  • R Jain
  • P Guttal
  • David W Parent, San Jose State University
Abstract
We show the design of a 6-bit decimation filter with a decimation factor 4 operating in sub threshold region. We find that the optimum Wp/Wn ratio for an inverter operating in the sub-threshold was 24 as measure by equalizing NMOS and PMOS transistors drives. At the maximum achievable operating frequency of 50 kHz the circuit uses 2.5 nW of power and occupies an area of 47 mum times 100 mum. TSMC 0.18 mum technology, with a supply voltage of 300 mV was used.
Publication Date
2006
Publisher Statement
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Citation Information
R Jain, P Guttal and David W Parent. "6 Bit Decimation Filter in Sub-threshold Region" Proceedings of the 16’th Bi Annual University, Government, Industry Microelectronics (UGIM) Symposium (2006)
Available at: http://works.bepress.com/david_parent/30/