A methodology is presented to evaluate the low power operation of a laterally diffused implanted MOS transistor. The transistor was fabricated in a standard 1.5 mum CMOS process by shifting the alignment between the p-well and the gate, resulting in an asymmetric channel doping and a lowly doped drift region. Fabrication was necessary to have detailed knowledge of the processing conditions and the resultant junction locations. Following the fabrication, devices were tested and shown to have improved performance as compared to standard CMOS transistors as a function of the heritage of the device.