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A 2-Mask NMOS Process Design Fabricate and Test Module for Use In Microelectronics Instruction and Process Development
Proceedings of the 16’th Bi Annual University, Government, Industry Microelectronics (UGIM) Symposium (2006)
  • David W Parent, San Jose State University
Abstract
We have developed a simplified 2-mask n-type metal oxide semiconductor (NMOS) transistor process design and verification module for electrical engineering students enrolled in the Microelectronic Manufacturing Methods class/laboratory at San Jose State University. We have run this module for three years and have found that the simplified process allows the students to learn more because they have the time to design the process fabricate and test in one semester. Student learning is also enhanced because it allows students to make and correct mistakes in the processing the devices. We have also found that the simplified process saves time in process development of more complex processes, by reducing the number of photolithography steps required to fabricate a transistor.
Publication Date
2006
Publisher Statement
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Citation Information
David W Parent. "A 2-Mask NMOS Process Design Fabricate and Test Module for Use In Microelectronics Instruction and Process Development" Proceedings of the 16’th Bi Annual University, Government, Industry Microelectronics (UGIM) Symposium (2006)
Available at: http://works.bepress.com/david_parent/28/