Skip to main content
Article
Hafnium Transistor Design for Neural Interfacing
Proceedings of the 30’th Annual Engineering in Medicine and Biology Society (EMBC) Conference (2008)
  • David W Parent, San Jose State University
  • E. Basham, San Jose State University
Abstract
A design methodology is presented that uses the EKV model and the gm/ID biasing technique to design hafnium oxide field effect transistors that are suitable for neural recording circuitry. The DC gain of a common source amplifier is correlated to the structural properties of a Field Effect Transistor (FET) and a Metal Insulator Semiconductor (MIS) capacitor. This approach allows a transistor designer to use a design flow that starts with simple and intuitive 1-D equations for gain that can be verified in 1-D MIS capacitor TCAD simulations, before final TCAD process verification of transistor properties. The DC gain of a common source amplifier is optimized by using fast 1-D simulations and using slower, complex 2-D simulations only for verification. The 1-D equations are used to show that the increased dielectric constant of hafnium oxide allows a higher DC gain for a given oxide thickness. An additional benefit is that the MIS capacitor can be employed to test additional performance parameters important to an open gate transistor such as dielectric stability and ionic penetration.
Publication Date
2008
Publisher Statement
SJSU users: use the following link to login and access the article via SJSU databases
Citation Information
David W Parent and E. Basham. "Hafnium Transistor Design for Neural Interfacing" Proceedings of the 30’th Annual Engineering in Medicine and Biology Society (EMBC) Conference (2008)
Available at: http://works.bepress.com/david_parent/22/