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Hafnium Transistor Process Design for Neural Interfacing
Proceedings of the 31’th Annual Engineering in Medicine and Biology Society (EMBC) Conference (2009)
  • David W Parent, San Jose State University
  • E J Basham, San Jose State University
Abstract
A design methodology is presented that uses 1-D process simulations of metal insulator semiconductor (MIS) structures to design the threshold voltage of hafnium oxide based transistors used for neural recording. The methodology is comprised of 1-D analytical equations for threshold voltage specification, and doping profiles, and 1-D MIS technical computer aided design (TCAD) to design a process to implement a specific threshold voltage, which minimized simulation time. The process was then verified with a 2-D process/electrical TCAD simulation. Hafnium oxide films (HfO) were grown and characterized for dielectric constant and fixed oxide charge for various annealing temperatures, two important design variables in threshold voltage design.
Publication Date
2009
Publisher Statement
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Citation Information
David W Parent and E J Basham. "Hafnium Transistor Process Design for Neural Interfacing" Proceedings of the 31’th Annual Engineering in Medicine and Biology Society (EMBC) Conference (2009)
Available at: http://works.bepress.com/david_parent/18/