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Removal of Threading Dislocations from Patterned Heteroepitaxial Semiconductors
Journal of Electronic Materials (1998)
  • X G Zhang, University of Connecticut
  • P Li, University of Connecticut
  • G Zhao, University of Connecticut
  • David W Parent, San Jose State University
  • F C Jain, University of Connecticut
  • J E Ayers, University of Connecticut
We have shown that threading dislocations can be removed from patterned heteroepitaxial semiconductors by glide to the sidewalls, which is driven by the presence of image forces. In principle, it should be possible to attain highly mismatched heteroepitaxial semiconductors which are completely free from threading dislocations, even though they are not pseudomorphic, by patterned heteroepitaxial processing. There are two basic approaches to patterned heteroepitaxial processing. The first involves selective area growth on a pre-patterned substrate. The second approach involves post-growth patterning followed by annealing. We have developed a quantitative model which predicts that there is a maximum lateral dimension for complete removal of threading dislocations by patterned heteroepitaxy. According to our model, this maximum lateral dimension is proportional to the layer thickness and increases monotonically with the lattice mismatch. For heteroepitaxial materials with greater than 1% lattice mismatch, our model predicts that practical device-sized threading dislocation-free regions may be realized by patterned heteroepitaxial processing.
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X G Zhang, P Li, G Zhao, David W Parent, et al.. "Removal of Threading Dislocations from Patterned Heteroepitaxial Semiconductors" Journal of Electronic Materials Vol. 27 (1998)
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