Skip to main content
Article
Investigation of Single pMOSFET Gate Oxide Degradation on NOR Logic Circuit Operability
McNair Scholars Research Journal
  • David Estrada
Publication Date
4-1-2007
Department
Electrical and Computer Engineering
Abstract
The impact of gate oxide degradation of a single pMOSFET on the performance of the CMOS NOR logic circuit has been examined using a switch matrix technique. A constant voltage stress of -4.0V was used to induce a low level of degradation to the 2.0nm gate oxide of the pMOSFET. Characteristics of the CMOS NOR logic circuit following gate oxide degradation are analyzed in both the DC and V-t domains. The NOR gate rise time increases by approximately 30%, which may lead to timing or logic errors in high frequency digital circuits. Additionally, the voltage switching point of the NOR logic circuit shifts by 9% which could affect operation of analog or mixed signal designs. This shift in NOR logic circuit performance is correlated to an increased channel resistance of the stressed pMOSFET.
Abstract Format
paragraphs formatted with HTML tags
Citation Information
David Estrada. "Investigation of Single pMOSFET Gate Oxide Degradation on NOR Logic Circuit Operability" (2007)
Available at: http://works.bepress.com/david_estrada/1/