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Article
TLP IV Characterization of a 40 Nm CMOS IO Protection Concept in the Powered State
Proceedings of the 38th Electrical Overstress/Electrostatic Discharge Symposium (2016, Garden Grove (Anaheim), CA)
  • Benjamin Orr
  • Krzysztof Domański
  • Harald Gossner
  • David Pommerenke, Missouri University of Science and Technology
Abstract
In this paper, the interaction between the ESD protection concept and a powered output driver in a 40 nm CMOS process are investigated and characterized by TLP. By using IO test chips designed for HBM and CDM validation, the IV behavior of the pin is measured with the driver placed into various states.
Meeting Name
38th Electrical Overstress/Electrostatic Discharge Symposium (2016: Sep. 11-16, Garden Grove (Anaheim), CA)
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
  • CMOS processs,
  • ESD protection,
  • I-V behavior,
  • IV characterization,
  • nocv2,
  • Output drivers,
  • Protection concepts,
  • Test chips,
  • CMOS integrated circuits
International Standard Book Number (ISBN)
978-158537289-8
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2016 ESD Association, All rights reserved.
Publication Date
10-1-2016
Citation Information
Benjamin Orr, Krzysztof Domański, Harald Gossner and David Pommerenke. "TLP IV Characterization of a 40 Nm CMOS IO Protection Concept in the Powered State" Proceedings of the 38th Electrical Overstress/Electrostatic Discharge Symposium (2016, Garden Grove (Anaheim), CA) Vol. 2016-October (2016) ISSN: 0739-5159
Available at: http://works.bepress.com/david-pommerenke/183/