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A Fast, Low-Power Logarithm Approximation with CMOS VLSI Implementation
Midwest Symposium on Circuits and Systems
  • Samuel L. SanGregory, Cedarville University
  • Charles Brothers
  • David Gallagher, Cedarville University
  • Raymond Siferd
Document Type
Conference Presentation
Location
Las Cruces, NM
Event Date
8-1-1999
Abstract

A new technique and CMOS VLSI implementation for computing approximate logarithms (base 2, and 10) for binary integers is presented. The approximation is performed using only combinational logic and requires no multiplications. Additionally, as implemented a ROM of only N*log2(N) bits is used to convert N bit integers. The maximum error of the approximation is 1.5% when the input value is 3, and decays exponentially to less than 0.5% for input values greater than 25.

Citation Information
Samuel L. SanGregory, Charles Brothers, David Gallagher and Raymond Siferd. "A Fast, Low-Power Logarithm Approximation with CMOS VLSI Implementation" Midwest Symposium on Circuits and Systems (1999)
Available at: http://works.bepress.com/david-gallagher/2/