To expose sufficient instruction-level parallelism (ILP) to make effective use of wide-issue superscalar and VLIW processor resources, the compiler must perform aggressive low-level code optimization and scheduling. However, ambiguous memory dependences can significantly limit the ...

It is demonstrated that optimization techniques incorporated within a silicon compiler for read-only memories (ROMs) can achieve significant yield, power, and speed improvements by minimizing the number of transistors, drains, and metal interconnections in the ...

A new technique and CMOS VLSI implementation for computing approximate logarithms (base 2, and 10) for binary integers is presented. The approximation is performed using only combinational logic and requires no multiplications. Additionally, as implemented ...

Modern warfare is placing an increasing reliance on global communications. Currently under development are several low Earth orbit (LEO) satellite systems that propose to deliver voice and data traffic to subscribers anywhere on the globe. ...

Sponsored by DISA, the SHF-DAMA standard addresses the warfighter's requirements for flexible, reliable, and efficient (technically and fiscally) satellite communications. The standard proposes a system supporting both packet data transfer and single-channel-per-carrier voice and data ...

To exploit instruction level parallelism, compilers for VLIW and superscalar processors often employ static code scheduling. However, the available code reordering may be severely restricted due to ambiguous dependences between memory instructions. This paper introduces ...

A new technique and CMOS VLSI implementation for computing approximate logarithms (base 2, and 10) for binary integers is presented. The approximation is performed using only combinational logic and requires no multiplications. Additionally, as implemented ...