Recently, the acoustic noise emanating from mobile devices becomes an important issue for user experience. The vibration of multilayer ceramic capacitors (MLCCs) mounted on printed circuit board (PCB) can transfer to the PCB and lead to acoustic noise. To mitigate singing cap acoustic noise, sometimes it has to trade off EMC/SI/PI performance during system design. So, simulation methodology is critical to predict critical acoustic issue and help design tradeoff. In this paper, a simulation methodology to provide design guideline for MLCC placement and PCB fixation with the aim to decrease board vibration is proposed. A finite element model of the multilayer PCB considering detailed copper/dielectric distribution of each layer is developed. Modal analysis is firstly performed to analyze the vibration characteristics of the bare PCB. Then the harmonic response of the board due to vibration excitation of MLCC is modeled. Based on the modal analysis result, the design guideline for MLCC placement and PCB fixation location can be established. The proposed guideline is validated through PCB harmonic response simulation.