An analytical methodology to calculate the probability density functions (PDFs) for the step pulse response of a single-ended buffer with arbitrary power-supply voltage fluctuations is proposed. To validate the theory, a silicon IC with noise-aggressing buffers and a victim buffer was designed, fabricated, and assembled in a printed circuit board (PCB). The overall power distribution network (PDN) of the IC and PCB was modeled from impedance measurements. The PDFs of the step pulse response of the victim buffer with power-supply voltage fluctuations were calculated and validated by comparisons with HSPICE and experimental results. The obtained PDFs due to power-supply voltage fluctuations could be combined with the statistical link simulation methods for quick estimation of bit error rate (BER).