This paper presents a novel methodology for on-chip power-noise modeling in the early stage of system-on-chip (SoC) design. Conventionally, the on-chip power-noise simulation is performed in 'placement and routing' design stage. Therefore, designers experience difficulty in applying the simulation results to improve power-noise performance because of the delivery time. The proposed methodology enables modeling of the dynamic current profile, without any geometry information and estimation of SoC power noise in the register-transfer-level design phase. Each SoC sub-block is defined as a unit simplified chip power model (SCPM), and the defined unit SCPMs are integrated into one SCPM, including multiblock characteristics. SCPM presents various types of current profiles to accurately predict the maximum current peak, and it includes the background current to prevent overestimation of the ac current. To improve the simulation accuracy, this paper proposes a voltage ripple measurement method that considers the SoC operating scenario. The simulation results of the SCPM are verified by the measurement results, and the SCPM methodology shows the correlation results of 7 and 18 mV on two test vehicles with a 1.1 V core voltage. In the chip-package design industry for electronic applications, the proposed methodology presents a design guide for the power delivery network, such as essential capacitance per location (e.g., chip, package, and printed circuit board) and the limit of the off-chip routing inductance. In addition, the forecast by the SCPM simulation shows that preactive design is available at the early stages of the design process.