An on-chip electromagnetic bandgap (EBG) structure is applied to protect a delay-locked loop (DLL) from simultaneous switching noise (SSN) coupling. The fabricated on-chip EBG structure has a low cut-off frequency of approximately 1 GHz. An accumulation-mode MOS capacitor is used to achieve a high layout efficiency for the MOS capacitor and therefore a large value of capacitance for the same layout area. The on-chip EBG structure is embedded in the middle of an on-chip power distribution network in which the DLL and an inverter chain acting as a noise source are connected. The measured results showed that the jitter at the DLL clock output is severely increased by the coupled SSN from the inverter chain. However, the operation of the inverter chain did not affect the jitter when the DLL was protected by the on-chip EBG structure.