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Presentation
Stochastic extraction of partial inductances in digital IC interconnect structures: 2D verification
VLSI Multilevel Interconnection Conference (2003)
  • K. Chatterjee
  • P. Matos
  • Benjamin G. Hawkins, San Jose State University
  • S. Jahanian
Publication Date
2003
Citation Information
K. Chatterjee, P. Matos, Benjamin G. Hawkins and S. Jahanian. "Stochastic extraction of partial inductances in digital IC interconnect structures: 2D verification" VLSI Multilevel Interconnection Conference (2003)
Available at: http://works.bepress.com/benjamin_hawkins/13/