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Article
Effects of Circuit-Level Stress on Inverter Performance and MOSFET Characteristics
2003 IEEE International Integrated Reliability Workshop Final Report
  • Nate Stutzke, Boise State University
  • Betsy J. Cheek, Boise State University
  • Santosh Kumar, Cypress Semiconductor
  • R. Jacob Baker, Boise State University
  • Amy J. Moll, Boise State University
  • William B. Knowlton, Boise State University
Document Type
Conference Proceeding
Publication Date
1-1-2003
Abstract
The effects of circuit-level stress on both inverter operation and MOSFET characteristics have been investigated. Individual MOSFETs, with gate oxide thickness of 3.2 nm and active dimensions of 25 µm × 25 µm, are connected in an inverter configuration off-wafer via a low-leakage switch matrix. Inverters are stressed with a ramped voltage stress (RVS) of various magnitudes to induce different degrees of gate oxide degradation. In addition, voltage transfer curves (VTCs) of degraded inverters are simulated using a new circuit model. At the transistor level, both the PMOSFET and the NMOSFET show increased gate leakage current up to eight orders of magnitude, severely reduced on-currents and transconductances (gm), and large threshold voltage (Vt) shifts of 100 mV or more. Different trends in inverter performance are observed following positive and negative stress. However, regardless of the stress polarity, circuit-level stress results in inverter performance degradation, such as reduced output swing, switching point shifts, and increased rise/fall times. After the largest positive RVS, the output voltage swing has decreased from 1.8 V fresh, to 1.54 V post-stress. Much larger changes in the inverter voltage (V-t) time domain performance are observed. The minimum output low voltage is similar to that of the VTC, but the rise time increased significantly enough that the output voltage is only pulled up to 660 mV (VDD = 1.8 V) before it switches low. In terms of circuit reliability, it may be possible for subsequent circuit stages to compensate for a few degraded devices, but increased rise/fall and delay times may cause timing issues in high-speed circuits. Furthermore, increased gate or off-stage leakage currents can potentially load previous circuit stages or result in increased power consumption.
Citation Information
Nate Stutzke, Betsy J. Cheek, Santosh Kumar, R. Jacob Baker, et al.. "Effects of Circuit-Level Stress on Inverter Performance and MOSFET Characteristics" 2003 IEEE International Integrated Reliability Workshop Final Report (2003)
Available at: http://works.bepress.com/amy_moll/31/