On-Chip 3D Inductors Using Thru-Wafer ViasIEEE Workshop on Microelectronics and Electron Devices (WMED)
Document TypeConference Proceeding
AbstractThree-dimensional (3D) inductors using high aspect ratio (10:1); thru-wafer via (TWV) technology in a complementary metal oxide semiconductor (CMOS) process have been designed, fabricated, and measured. The inductors were designed using 500 μm tall vias, with the number of turns ranging from 1 to 20 in both wide and narrow-trace width-to-space ratios. Radio frequency characterization was studied with emphasis upon de-embedding techniques and the resulting effects. The open, short, thru de-embedding (OSTD) technique was used to measure all devices. The highest quality factor (Q) measured was 11.25 at 798 MHz for a 1-turn device with a self-resonant frequency (fsr) of 4.4 GHz. The largest inductance (L) measured was 45 nH on a 20-turn, wide-trace device with a maximum Q of 4.25 at 732 MHz. A 40% reduction in area is achieved by exploiting the TWV technology when compared to planar devices. This technology shows promising results with further development and optimization.
Citation InformationGary VanAckern, R. Jacob Baker, Amy J. Moll and Vishal Saxena. "On-Chip 3D Inductors Using Thru-Wafer Vias" IEEE Workshop on Microelectronics and Electron Devices (WMED) (2012)
Available at: http://works.bepress.com/amy_moll/27/