Drop Test Reliability of Lead-free Chip Scale PackagesProceedings of the 58th IEEE Electronics Components and Technology Conference: Lake Buena Vista, FL
AbstractThis paper presents the drop test reliability of 0.5 mm pitch lead-free chip scale packages (CSPs). Fifteen 0.5 mm pitch CSPs were assembled on a standard JEDEC drop reliability test board with Sn3.0Ag0.5Cu lead-free solder. Eight boards were edge-bonded with a UV-cured acrylic; eight boards were edge- bonded with a thermal-cured epoxy; and twelve boards were assembled without edge bonding. Half of the edge-bonded test boards were subjected to drop tests at a peak acceleration of 1500 G with a pulse duration of 0.5 ms, and the other half subjected to drop tests at a peak acceleration of 2900 G with a pulse duration of 0.3 ms. Half of the test boards without edge bonding were subjected to drop tests at a peak acceleration of 900 G with a pulse duration of 0.7 ms, and the other half subjected to drop tests at a peak acceleration of 1500 G with a pulse duration of 0.5 ms. Two drop test failure detection systems were used in this study to monitor the failure of solder joints: a high-speed resistance measurement system and a post-drop static resistance measurement system. The high-speed resistance measurement system, which has a scan frequency of 50 KHz and a 16-bit signal width, is able to detect intermittent failures during the short drop impact duration. Statistics of the number of drops to failure for the 15 component locations on each test board are reported. The effect of component position on drop test reliability is discussed. The test results show that the drop test performance of edge-bonded CSPs is five to eight times better than the CSPs without edge bonding. However, the drop test reliability of edge-bonded CSPs with the thermal-cured epoxy is different from that with edge-bonded CSPs with the UV-cured acrylic. The solder crack location and crack area are characterized with the dye penetrant method. The fracture surfaces are studied using scanning electron microscopy (SEM).
Citation InformationAndrew Farris, Jianbiao Pan, Albert Liddicoat, Brian J. Toleno, et al.. "Drop Test Reliability of Lead-free Chip Scale Packages" Proceedings of the 58th IEEE Electronics Components and Technology Conference: Lake Buena Vista, FL (2008) p. 1173 - 1180
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