Test chips incorporating piezoresistive stress sensors are powerful tools for experimental stress analysis of electronic packages. Sensor rosettes on (111) silicon offer the unique ability to characterize the complete stress state on the surface of a die. In this work, the design and calibration of two second generation (111) stress sensor test chips are described. The first test chip contains perimeter pads suitable for wire bond packages, and the second test chip contains an area pad array suitable for flip-chip applications. The rosettes on the fabricated (111) silicon sensor die have been calibrated using four-point bending, hydrostatic, and wafer level calibration methods. The test chips are currently being utilized to characterize stress in a variety of plastic encapsulated and flip-chip packages