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Design and Calibration of Optimized (111) Silicon Stress Sensing Test Chips
Advances in electronic packaging, 1997 : proceedings of the Pacific Rim/ASME International Intersociety Electronic & Photonic Packaging Conference, INTERpack '97
  • Jeffrey C. Suhling
  • Richard C. Jaeger
  • Shun-Tien Lin
  • Ahsan Mian, Wright State University - Main Campus
  • Robert A. Cordes
  • B. M. Wilamowski
Document Type
Conference Proceeding
Publication Date
1-1-1997
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Abstract

The (111) surface of silicon offers unique advantages for fabrication of piezoresistive stress sensors. Resistive sensor elements fabricated on this particular surface respond to all six components comprising the state of stress. Hence, a multi-element rosette has the capability of measuring the complete stress state at a point in the material. Four of the stress component measurements are temperature compensated. This is in contrast to standard sensors fabricated on traditional (100) silicon, where only four stress components can be measured (two in a temperature compensated manner). Several generations of (111) silicon test chips have been designed, fabricated, and calibrated to demonstrate the capabilities of these advanced sensors.

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Paper presented at INTERpack ’97, Kohala, HI, June 15-19, 1997.

Citation Information
Jeffrey C. Suhling, Richard C. Jaeger, Shun-Tien Lin, Ahsan Mian, et al.. "Design and Calibration of Optimized (111) Silicon Stress Sensing Test Chips" Advances in electronic packaging, 1997 : proceedings of the Pacific Rim/ASME International Intersociety Electronic & Photonic Packaging Conference, INTERpack '97 Vol. 19 (1997) p. 1723 - 1729 ISSN: 0791815595
Available at: http://works.bepress.com/ahsan-mian/16/