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Method and System for Error Correction in Flash Memory: Patent Application
(2007)
Abstract
A solid state non-volatile memory unit. The memory unit
includes a multi-level solid state non-volatile memory array
adapted to store data characterized by a ?rst number of
digital levels. The memory unit also includes an analog-to
digital converter having an input and an output. The input of
the analog-to-digital converter is adapted to receive data
from the multi-level solid state non-volatile memory array.
The output of the analog-to-digital converter is adapted to
output a digital signal characterized by a second number of
digital levels greater than the ?rst number of digital levels.
Disciplines
Publication Date
July 26, 2007
Comments
This is a patent application filed on November 8, 2006. Publication number US 2007/0171730 A1. Application number 11/598,117.
Citation Information
Aditya Ramamoorthy, Zining Wu and Pantas Sutardja. "Method and System for Error Correction in Flash Memory: Patent Application" (2007) Available at: http://works.bepress.com/aditya-ramamoorthy/8/