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Method and System for Error Correction in Flash Memory
(2013)
Abstract
A multi-level solid state non-volatile memory array has
memory cells that store data using a ?rst number of digital
levels. A controller of the memory array encodes a series of
data bits to generate a series of encoded data bits, and converts
the series of encoded data bits into a series of data symbols.
The controller sends, to the memory array, a stored series of
data symbols based on the series of data symbols for storage
in a memory cell of the multi-level solid state non-volatile
memory array. The controller generates an output signal
based on data associated With the stored series of data sym
bols. The output signal is characterized by a second number of
digital levels greater than the ?rst number of digital levels.
The controller outputs a series of output data symbols based
on the output signal.
Disciplines
Publication Date
June 25, 2013
Comments
This is a patent filed on November 15, 2010. Publication number US 8,473,812 B2. Application number 12/946,520. Assignee: Marvell World Trade Ltd.
Citation Information
Aditya Ramamoorthy, Zining Wu and Pantas Sutardja. "Method and System for Error Correction in Flash Memory" (2013) Available at: http://works.bepress.com/aditya-ramamoorthy/7/