Full-Feedforward K-Delta-1-Sigma Modulator
4th Annual Austin Conference on Integrated Circuits & Systems, Oct. 26-27, 2009.
This paper discusses the design of a second-order full-feedforward K-Delta-1-Sigma (KD1S) modulator with a fast feedback loop around the quantizer. The proposed second-order KD1S modulator employs inherent interleaving with shared op-amp and K-quantizing paths that has the potential to achieve significantly higher conversion bandwidths than traditional delta-sigma ADCs. A second-order full-feedforward ADC using an 8-path KD1S modulator and ideal components achieves an SNR of 70 dB (or 12-bit resolution) for a conversion bandwidth of 6.25 MHz with 800 MHz effective sampling rate. For the same bandwidth, the proposed second-order KD1S modulator is simulated in 130 nm CMOS achieving 58 dB SNR (or 10-bit resolution).
Kaijun Li, Vishal Saxena, Geng Zheng, and R. Jacob Baker. "Full-Feedforward K-Delta-1-Sigma Modulator" 4th Annual Austin Conference on Integrated Circuits & Systems (2009).
Available at: http://works.bepress.com/vishal_saxena/8
This document is currently not available here.