Jianbiao Pan Copyright (c) 2011 All rights reserved. http://works.bepress.com/pan Recent documents in Jianbiao Pan en-us Sat, 03 Dec 2011 01:34:09 PST 3600 Effect of Gold Content on the Reliability of SnAgCu Solder Joints http://works.bepress.com/pan/38 http://works.bepress.com/pan/38 Thu, 01 Dec 2011 10:55:45 PST Electroplated Ni/Au over Cu is a popular metallization for printed circuit board finish as well as for component leads, especially wire-bondable high-frequency packages, where the gold thickness requirement for wire bonding is high. The general understanding is that less than 3 wt% of Au is acceptable in SnPb solder joints. However, little is known about the effect of Au content on the reliability of SnAgCu solder joints. The purpose of this paper is to determine the acceptable level of Au in SAC305 solder joints. Three different package platforms with different Au thicknesses were assembled on boards with two different Au thicknesses using a standard surface mount assembly line in a realistic production environment. The assembled boards were divided into three groups: as-built, isothermally aged at 125 °C for 30 days, and isothermally aged at 125 °C for 56 days. All boards were then subjected to accelerated mechanical reliability tests including random vibration and drop testing. The results show that solder joints with over 10 wt% Au are unacceptable. If Cu is available to dissolve in the solder joint, then an Au content under 5 wt% will not significantly degrade the reliability of the solder joint. When Ni layers are present on both the board and the component sides of the interface, this limits the ability of Cu to dissolve into the solder joint, and hence an Au content under 3 wt% is acceptable. The failure mechanism for solder joints with high Au content is fractures through the AuSn4 intermetallic compound. Additional findings confirmed that there is a danger of placing parts near high-stress areas and that a high level of voiding reduced reliability.

]]> Jianbiao Pan et al. Articles A Study of Solder Joint Failure Criteria http://works.bepress.com/pan/37 http://works.bepress.com/pan/37 Fri, 04 Nov 2011 15:46:46 PDT One of the challenges in an experimental study of solder joint reliability is to determine when cracks occur in a solder joint or when a solder joint fails. Cracks in a real solder joint are difficult to identify using an X-Ray system. Cross-sectioning and scanning electron microscopy (SEM) is a destructive method. A common non-destructive test method is to monitor resistance increase in a solder joint or a daisy-chain. However, no scientific research has been done in establishing the relationship between the crack area of an interconnection and the change in resistance of the interconnection. This paper proposes a method of defining failure criteria as the resistance increase in a solder joint exceeding a threshold. The threshold is determined by k times the range over the natural variation in resistance measured by a measurement system. The natural variation by random cause is judged using X-bar and R charts. The principles of defining failure criteria are to be able to detect failure of solder joints as early as possible with minimum false detection due of measurement system error/variation. An experimental study confirmed that a full crack of an interconnection occurs when the increase of resistance in the interconnection is 10 times the natural variation of resistance change. The results of this study could be used to narrow the definition of failure in consensus standards IPC 9701A, JESD22-B111, and IPC/JEDEC-9702.

]]> Jianbiao Pan et al. Conference Proceedings Effect of Gold Content on the Microstructural Evolution of SAC305 Solder Joints Under Isothermal Aging http://works.bepress.com/pan/36 http://works.bepress.com/pan/36 Fri, 04 Nov 2011 15:46:42 PDT Au over Ni on Cu is a widely used printed circuit board (PCB) surface finish, under bump metallization (UBM), and component lead metallization. It is generally accepted that less than 3 wt.% Au in Sn-Pb solder joints inhibits formation of detrimental intermetallic compounds (IMC). However, the critical limit for Au content in Pb-free solder joints is not well established. Three surface-mount package platforms, one with a matte Sn surface finish and the others with Ni/Au finish, were soldered to Ni/Au-finished PCB using Sn-3.0Ag- 0.5Cu (SAC305) solder, in a realistic manufacturing setting. The assembled boards were divided into three groups: one without any thermal treatment, one subjected to isothermal aging at 125oC for 30 days, and the third group aged at 125oC for 56 days. Representative solder joints were cross-sectioned and analyzed using scanning electron microscopy (SEM) and energy-dispersive x-ray spectroscopy (EDX) to investigate the evolution of the solder joint morphology as a function of Au content and isothermal aging. It was found that, if Cu is available to dissolve in the solder joint, the migration of AuSn4 from the bulk to the interface as a result of thermal aging is mitigated.

]]> Mike Powers et al. Articles Effect of Gold Content on the Reliability of SnAgCu Solder Joints http://works.bepress.com/pan/35 http://works.bepress.com/pan/35 Mon, 01 Aug 2011 14:30:55 PDT Electroplated Ni/Au over Cu is a popular metallization for PCB finish as well as for component leads, especially wire-bondable high frequency packages, where the gold thickness requirement for wirebonding is high. The general understanding is that less than 3 wt% of Au is acceptable in SnPb solder joints. However, little is known about the effect of Au content on the reliability of SnAgCu solder joints. The purpose of this study is to determine the acceptable level of Au in SAC305 solder joints. Three different package platforms with different Au thicknesses were assembled on boards with two different Au thicknesses using a standard surface mount assembly line in a realistic production environment. The assembled boards were divided into three groups: as-built, isothermally aged at 125°C for 30 days, and isothermally aged at 125°C for 56 days. All boards were then subjected to accelerated mechanical reliability tests including random vibration and drop testing. The results show that solder joints with over 10 wt% Au are unacceptable. If Cu is available to dissolve in the solder joint, then an Au content under 5 wt% will not significantly degrade the reliability of the solder joint. When Ni layers are present on both the board and component sides of the interface, this limits the ability of Cu to dissolve into the solder joint and hence an Au content under 3 wt% is acceptable. The failure mechanism for solder joints with high Au content is fractures through the AuSn4 IMC. Our comprehensive long-term reliability study did not confirm the finding by Ho et al. (2002) that the weak interface between (Au, Ni)Sn4 and Ni3Sn4 results in brittle interfacial failure. Additional findings confirmed the danger of placing parts near high stress areas and that a high level of voiding reduced reliability.

]]> Jianbiao Pan et al. Conference Proceedings Development and Assessment of a PCB Layout and Manufacturong Laboratory Module in Introductory Electric Circuits for EE and Non-EE Majors http://works.bepress.com/pan/34 http://works.bepress.com/pan/34 Mon, 18 Oct 2010 02:13:57 PDT In standard introductory electric circuits laboratories for electrical engineering (EE) majors and non-EE majors, prototype boards are typically used to construct and test electric circuits. Students typically do not learn how to design and manufacture Printed Circuit Boards (PCB) that are commonly used in more sophisticated design projects and other engineering applications. This paper will present the development and assessment of a PCB layout and manufacturing laboratory module that has been used in introductory electric circuits laboratories for EE and non-EE majors. The feasibility of integrating the new PCB layout and manufacturing module into the electric circuit course will be discussed. An experiment has been designed and conducted to assess the impact of the PCB module. A survey with questions from the Motivated Strategies for Learning Questionnaire (MSLQ) supplemented with additional questions was used to measure students’ motivation and the impact of the PCB module on student learning. In Winter quarter of 2009 at Cal Poly, two lab sessions for sophomore and junior non-EE engineering majors were taught by an instructor with an experimental group that designed a real PCB for one of their circuit design experiments and a control group that implemented all of the experiments using prototype boards. In Spring quarter of 2009 at Cal Poly, two lab sessions for EE majors at the sophomore level were offered by the same instructor with an experimental group that designed and built a PCB for one of their circuit design experiments and a control group that performed all experiments using prototype boards. Data have been collected and analyzed for these four student groups. Results indicate the inclusion of the PCB module did not impact the student’s ability to achieve any of the course or laboratory learning objectives. Though no statistically significant difference in student’s motivation was found between the experimental group and the control group, the results strongly indicate that students enjoyed the introduction of the PCB design module. Furthermore, students report they have a higher confidence in their ability to design printed circuit boards and they are more likely to design PCBs in other course projects as part of their senior projects.

]]> Albert Liddicoat et al. Conference Proceedings Assessing Curriculum Improvement Through Senior Projects http://works.bepress.com/pan/33 http://works.bepress.com/pan/33 Mon, 18 Oct 2010 02:13:54 PDT Senior project and/or capstone design courses are intended to provide a culminating design experience for students and to demonstrate their understanding of engineering knowledge and their ability to apply that knowledge to practical problems. It is expected that the quality and attributes of students’ senior design projects can be used as a good measure of determining how well the curriculum prepares students to engage in engineering design as well as a measure of faculty teaching and student learning. This paper reports the results of a study designed to assess whether the new computer engineering curriculum implemented at Cal Poly over the previous five years has had a positive impact in preparing students for engineering design through measuring the quality and complexity of senior design projects. A randomized complete block design was used in the study. Ten senior projects each were randomly selected from the population of three groups: computer engineering senior projects completed in the 2002-2003 academic year, computer engineering senior projects completed in the 2007-2008 academic year, and electrical engineering senor projects completed in the 2007-2008 academic year. A senior project evaluation rubric was developed to assess the quality and complexity of the senior projects. Members from the Computer Engineering Industrial Advisory Board used the rubric to score the randomly selected senior projects. The scores assigned by the advisory board members were compared to the letter grades assigned by faculty advisors for these senior projects. The results of the analysis show that the overall quality of computer engineering senior projects improved from academic year 2002-2003 to academic year 2007-2008. However, there is a statistically significant difference in the overall senior project grades assigned between faculty advisors as compared to senior project scores assigned by the advisory board members. The results also indicate that the rubric developed from this study is robust since different evaluators did not have a statistically significant effect on the grading of senior projects.

]]> Jianbiao Pan et al. Conference Proceedings The Effect of Ultrasonic Frequency on Gold Wire Bondability and Reliability http://works.bepress.com/pan/32 http://works.bepress.com/pan/32 Mon, 21 Sep 2009 15:31:28 PDT This paper presents a systematic study on the effect of 120 KHz ultrasonic frequency on the bondability and reliability of fine pitch gold wire bonding to pads over an organic substrate with gold metallizations. The study was carried out on a thermosonic ball bonder that is allowed to easily switch between ultrasonic frequencies of 60 KHz and 120 KHz by changing the ultrasonic transducer and the ultrasonic generator. Bonding parameters were optimized through the design of experimental methodology for four different cases: 25.4 mm wire at 60 kHz, 25.4 mm wire at 120 kHz, 17.8 mm wire at 60 kHz, and 17.8 mm wire at 120 kHz. The integrity of wire bonds was evaluated by six response variables. The optimized bonding process was selected according to the multiattribute utility theory. With the optimized bonding parameters developed on one metallization for each of the four cases, 8,100 bonds were made on five different metallizations. The samples were then divided into three groups. The first group was subjected to humidity at 85º C/85% RH for up to 1,000 h. The second group was subjected to thermal aging at 125ºC for up to 1,000 h. The third group was subjected to temperature cycling from -55ºC to +125ºC with 1 h per cycle for up to 1,000 cycles. The bond integrity was evaluated through the wire pull and the ball shear tests immediately after bonding, and after each 150, 300, 500, and 1,000 h time interval in the reliability tests. Results show that 120 kHz frequency requires less ultrasonic power than 60 kHz when all other parameters are equal. The results also indicate that bonding at 120 kHz frequency is less sensitive to different metallizations than bonding at 60 kHz. All three reliability tests do not negatively affect the bond integrity of Au wire bonds on a variety of Au metallizations for both frequencies. Furthermore, as the reliability test time increases, both pull and shear strengths of Au wire bonds on Au pads increase.

]]> Jianbiao Pan et al. Articles Effects of Reflow Profile and Thermal Conditioning on Intermetallic Compound Thickness for SnAgCu Soldered Joints http://works.bepress.com/pan/30 http://works.bepress.com/pan/30 Mon, 21 Sep 2009 15:29:37 PDT Purpose – The purpose of this paper is to investigate the effects of reflow time, reflow peak temperature, thermal shock and thermal aging on the intermetallic compound (IMC) thickness for Sn3.0Ag0.5Cu (SAC305) soldered joints.
Design/methodology/approach – A four-factor factorial design with three replications is selected in the experiment. The input variables are the peak temperature, the duration of time above solder liquidus temperature (TAL), solder alloy and thermal shock. The peak temperature has three levels, 12, 22 and 32°C above solder liquidus temperatures (or 230, 240 and 250°C for SAC305 and 195, 205, and 215°C for SnPb). The TAL has two levels, 30 and 90 s. The thermally shocked test vehicles are subjected to air-to-air thermal shock conditioning from -40 to 125°C with 30 min dwell times (or 1 h/cycle) for 500 cycles. Samples both from the initial time zero and after thermal shock are cross-sectioned. The IMC thickness is measured using scanning electron microscopy. Statistical analyses are conducted to compare the difference in IMC thickness growth between SAC305 solder joints and SnPb solder joints, and the difference in IMC thickness growth between after thermal shock and after thermal aging.
Findings – The IMC thickness increases with higher reflow peak temperature and longer time above liquidus. The IMC layer of SAC305 soldered joints is statistically significantly thicker than that of SnPb soldered joints when reflowed at comparable peak temperatures above liquidus and the same time above liquidus. Thermal conditioning leads to a smoother and thicker IMC layer. Thermal shock contributes to IMC growth merely through high-temperature conditioning. The IMC thickness increases in SAC305 soldered joints after thermal shock or thermal aging are generally in agreement with prediction models such as that proposed by Hwang.
Research limitations/implications – It is still unknown which thickness of IMC layer could result in damage to the solder.
Practical implications – The IMC thickness of all samples is below 3 µm for both SnPb and SAC305 solder joints reflowed at the peak temperature ranging from 12 to 32°C above liquidus temperature and at times above liquidus ranging from 30 to 90 s. The IMC thickness is below 4 µm after subjecting to air-to-air thermal shock from -40 to 125°C with 30 min dwell time for 500 cycles or thermal aging at 125°C for 250 h.
Originality/value – The paper reports experimental results of IMC thickness at different thermal conditions. The application is useful for understanding the thickness growth of the IMC layer at various thermal conditions.

]]> Jianbiao Pan et al. Articles Backward and Forward Compatibility http://works.bepress.com/pan/31 http://works.bepress.com/pan/31 Mon, 21 Sep 2009 15:29:37 PDT In response to the European Union (EU) Restriction of Hazardous Substances (RoHS) and other countries’ impending lead-free directives, the electronics industry is moving toward lead-free soldering. Total lead-free soldering requires not only lead-free solder paste but also lead-free printed circuit board (PCB) finish and lead-free component/packages. Transitioning tin-lead (SnPb) soldering to totally lead-free soldering is a complex issue and involves movement of the whole electronics industry supply chain. In reality, there is a transition period.

]]> Jianbiao Pan et al. Contributions to Books Finding and Optimising the Key Factors for the Multiple-Response Manufacturing Process http://works.bepress.com/pan/29 http://works.bepress.com/pan/29 Tue, 07 Jul 2009 15:24:00 PDT With the advent of modern technology, manufacturing processes became so sophisticated that a single quality characteristic cannot reflect the true product quality. Thus, it is essential to perform the key factor analysis for the manufacturing process with multiple-input (factors) and multiple-output (responses). In this paper, an integrated approach of using the desirability function in conjunction with the Mahalanobis-Taguchi-Gram Schmit (MTGS) system is proposed in order to find and optimise the key factors for a multiple-response manufacturing process. The aim of using the MTGS method is to standardise and orthogonalise the multiple responses so that the Mahalanobis distance for each run can be calculated and the multi-normal assumption for the correlated responses can be relaxed. A realistic example of the solder paste stencil printing process is then used to demonstrate the usefulness of our proposed approach in a practical application.

]]> Jeh-Nan Pan et al. Articles Optimization of Engineering Tolerance Design Using Revised Loss Functions http://works.bepress.com/pan/28 http://works.bepress.com/pan/28 Tue, 07 Jul 2009 15:23:59 PDT Engineering tolerance design plays an important role in modern manufacturing. Both symmetric and asymmetric tolerances are common in many manufacturing processes. Recently, various revised loss functions have been proposed for overcoming the drawbacks of Taguchi's loss function. In this article, Kapur's economic tolerance design model is modified and the economic specification limits for both symmetric and asymmetric losses are established. Three different loss functions are compared in the optimal symmetric and asymmetric tolerance design: a revised Taguchi quadratic loss function, an inverted normal loss function and a revised inverted normal loss function. The relationships among the three loss functions and process capability indices are established. A numerical example is given to compare the economic specification limits established by using the three loss functions. The results suggest that the revised inverted normal loss function be used in determining economic specification limits.

]]> Jeh-Nan Pan et al. Articles Drop Impact Reliability of Edge-Bonded Lead-Free Chip Scale Packages http://works.bepress.com/pan/27 http://works.bepress.com/pan/27 Tue, 07 Jul 2009 14:44:24 PDT This paper presents the drop test reliability results for edge-bonded 0.5 mm pitch lead-free chip scale packages (CSPs) on a standard JEDEC drop reliability test board. The test boards were subjected to drop tests at several impact pulses, including a peak acceleration of 900 Gs with a pulse duration of 0.7 ms, a peak acceleration of 1500 Gs with a pulse duration of 0.5 ms, and a peak acceleration of 2900 Gs with a pulse duration of 0.3 ms. A high-speed dynamic resistance measurement system was used to monitor the failure of the solder joints. Two edge-bond materials used in this study were a UV-cured acrylic and a thermal-cured epoxy material. Tests were conducted on CSPs with edge-bond materials and CSPs without edge bonding. Statistics of the number of drops-to-failure for the 15 component locations on each test board are reported. The test results show that the drop test performance of edge-bonded CSPs is five to eight times better than the CSPs without edge bonding. Failure analysis was performed using dye-penetrant and scanning electron microscopy (SEM) methods. The most common failure mode observed is pad lift causing trace breakage. Solder crack and pad lift failure locations are characterized with the dye-penetrant method and optical microscopy.

]]> Andrew Farris et al. Articles Lead-free Solder Joint Reliability – State of the Art and Perspectives http://works.bepress.com/pan/26 http://works.bepress.com/pan/26 Wed, 14 Jan 2009 14:23:51 PST There is an increasing demand in replacing tin-lead (Sn/Pb) solders with lead-free solders in the electronics industry due to health and environmental concern. The European Union recently passed a law to ban the use of lead in electronic products. The ban will go into effect in July of 2006. The Japanese electronics industry has worked to eliminate lead from consumer electronic products for several years. Although currently there are no specific regulations banning lead in electronics devices in the United States, many companies and consortiums are working on lead-free solder initiatives including Intel, Motorola, Agilent Technologies, General Electric, Boeing, NEMI and many others to avoid a commercial disadvantage.

The solder joints reliability not only depends on the solder joint alloys, but also on the component metallization and PCB metallization. Reflow profile has significant impact on lead-free solder joint performance also because it influences wetting and microstructure of the solder joint. Majority researchers use temperature cycling for accelerated reliability testing since the solder joint failure mainly comes from thermal stress due to CTE mismatch. A solder joint failure could be caused by crack initiation and growth or by macroscopic solder facture. There are conflicting views of the reliability comparison between lead-free solders and tin-lead solders.

This paper first reviews lead-free solder alloys, lead-free component finishes, and lead-free PCB surface finishes. Tin whisker issue is also discussed. Then the lead-free solder joint testing methods are presented; finite element modeling of lead-free solder joint reliability is reviewed; and experimental data comparing lead-free and tin-lead solder joint reliability are summarized. Finally the paper gives perspectives of transitions to a totally lead-free manufacturing.

]]> Jianbiao Pan et al. Conference Proceedings Screen Printing Process Design of Experiments for Fine Line Printing of Thick Film Ceramic Substrates http://works.bepress.com/pan/24 http://works.bepress.com/pan/24 Wed, 14 Jan 2009 14:23:14 PST Screen printing has been the dominant method of thick film deposition because of its low cost. Many experiments in industry have been done and many models of the printing process have been developed since the 1960’s. With a growing need for denser packaging and a drive for higher pin count, screen printing has been refined to yield high resolution prints. However, fine line printing is still considered by industry to be difficult. In order to yield high resolution prints with high first pass yields and manufacturing throughput, the printing process must be controlled stringently.

This paper focuses on investigating the effect of manufacturing process parameters on fine line printing through the use of statistical design of experiments (DOE). The process parameters include print speed, squeegee hardness, squeegee pressure, and snap-off distance. Response variables are mean width and standard deviation of 10 mil, 8 mil, and 5 mil lines in both parallel and perpendicular directions relative to the squeegee travel direction. It is concluded that the squeegee hardness has a statistically significant effect on both directions, while the squeegee speed has an effect only on the parallel direction. The implementation procedures of the experimental design are presented. The analysis of a 2k factorial design with center points pertaining to the fine line printing experiment is discussed in detail.

]]> Jianbiao Pan et al. Conference Proceedings Investigation of the Lead-free Solder Joint Shear Performance http://works.bepress.com/pan/25 http://works.bepress.com/pan/25 Wed, 14 Jan 2009 14:22:51 PST Reflow profile has significant impact on solder joint performance because it influences wetting and microstructure of the solder joint. The purpose of this study is to investigate the effects of reflow profile and thermal shock on the shear performance of eutectic SnPb (SnPb) and Sn3.0Ag0.5Cu (SAC305) solder joints. Test boards were assembled with four different sized surface mount chip resistors (1206, 0805, 0603 and 0402). Nine reflow profiles for SAC 305 and nine reflow profiles for SnPb were developed with three levels of peak temperature (12ºC, 22ºC, and 32ºC above solder liquidus temperature, or 230ºC, 240ºC, and 250ºC for SAC 305; and 195ºC, 205ºC, and 215ºC for SnPb) and three levels of time above solder liquidus temperature (30 sec., 60 sec., and 90 sec.). Half of the test vehicles were then subjected to air-to-air thermal shock conditioning from -40 to 125°C. The shear force data were analyzed using the Analysis of Variance (ANOVA). The fracture surfaces were studied using a Scanning Electron Microscopy (SEM) with Energy Dispersive Spectroscopy (EDS). It was found that thermal shock degraded both SnPb and SnAgCu joints shear strength, and that the effect of thermal shock on solder joint shear strength is much more significant than that of reflow profile. The SnAgCu solder joints have weaker shear strength than the SnPb solders. SnAgCu solder joint after thermal shock retains more of its shear strength than that of SnPb for small components and vice versa for larger components.

]]> James Webster et al. Conference Proceedings Designing and Manufacturing Microelectronic Packages for High-Power Light-Emitting Diodes http://works.bepress.com/pan/23 http://works.bepress.com/pan/23 Thu, 08 Jan 2009 14:11:46 PST A new microelectronic package was designed for a high-power light-emitting diode (LED). The objective was to build a package that enables the LED to operate with currents as high as 2 Amps. An innovative thin-film interface has been developed to electrically connect the cathode of the LED die to a 22AWG Cu wire. This thin-film interface is wirebondable and solderable, and consists of three layers: Au, Ni93/V7, and Si. Four 1 mil Au wirebonds, supporting 2A of maximum current, connect the Au thin-film to the LED die cathode. Sn96Ag4 solder is used for connecting the Ni93/V7 thin-film to the 22AWG Cu wire. To provide an electrical, mechanical and thermal platform for the anode of the LED die, a sub-assembly was developed. This sub-assembly utilizes a Cu substrate on which the anode of the LED die is attached with Au80Sn20 solder. The LED die, thin-film interface and Cu substrate integrate into the sub-assembly, which then solders onto a Cu heatsink. Electrical current flows into the heatsink, through the LED, across the thin-film interface, then out the Cu wire. All-metal interfaces from the LED anode to the heatsink provide a thermally conductive path. However, testing results show that the LED fails with currents of 815 mAmps or less. It appears that the failure was caused by thermal management within the die and is not due to the design of the package.

]]> Brian Wright et al. Conference Proceedings Board Level Failure Analysis of Chip Scale Package Drop Test Assemblies http://works.bepress.com/pan/22 http://works.bepress.com/pan/22 Thu, 08 Jan 2009 14:11:40 PST This paper presents the failure analysis results of board level drop tests. In this study, the test vehicle was designed according to the requirements of the Joint Electron Device Engineering Council (JEDEC) drop test board. The test vehicle was assembled with 15 chip scale packages (CSPs) each having 228 daisy-chained 0.5 mm pitch solder joints using Sn-3.0 wt% Ag-0.5 wt% Cu (SAC305) lead free solder. Assemblies were drop tested using three different peak accelerations of 900 G, 1500 G, 2900 G, with 0.7 ms, 0.5 ms, and 0.3 ms pulse durations, respectively. Scanning electron microscopy (SEM) with energy dispersive spectroscopy and dye-penetrant methods were applied to investigate the failure locations and the failure modes. The failure modes and solder joint locations were mapped. Failure analysis showed that pad cratering was the most common failure mode and that this led to trace cracking on the board side. Trace cracking was the second most common failure mode. Solder joint cracking was also observed on the board side near the intermetallic layer, which was the third most common failure mode. The results imply that the solder joint is more reliable than the printed circuit board during drop test.

]]> Nicholas Vickers et al. Conference Proceedings Investigation of the Lead-free Solder Joint Shear Performance http://works.bepress.com/pan/21 http://works.bepress.com/pan/21 Thu, 08 Jan 2009 14:11:36 PST Reflow profile has significant impact on solder joint performance because it influences wetting and microstructure of the solder joint. The purpose of this study is to investigate the effects of reflow profile and thermal shock on the shear performance of eutectic SnPb (SnPb) and Sn3.0Ag0.5Cu (SAC305) solder joints. Test boards were assembled with four different sized surface mount chip resistors (1206, 0805, 0603 and 0402). Nine reflow profiles for SAC 305 and nine reflow profiles for SnPb were developed with three levels of peak temperature (12ºC, 22ºC, and 32ºC above solder liquidus temperature, or 230ºC, 240ºC, and 250ºC for SAC 305; and 195ºC, 205ºC, and 215ºC for SnPb) and three levels of time above solder liquidus temperature (30 sec., 60 sec., and 90 sec.). Half of the test vehicles were then subjected to air-to-air thermal shock conditioning from -40 to 125°C. The shear force data were analyzed using the Analysis of Variance (ANOVA). The fracture surfaces were studied using a Scanning Electron Microscopy (SEM) with Energy Dispersive Spectroscopy (EDS). It was found that thermal shock degraded both SnPb and SnAgCu joints shear strength, and that the effect of thermal shock on solder joint shear strength is much more significant than that of reflow profile. The SnAgCu solder joints have weaker shear strength than the SnPb solders. The SnAgCu solder joint after thermal shock retains more of its shear strength than that of SnPb for small components and vice versa for larger components.

]]> James Webster et al. Articles Drop Impact Dynamic Response Study of JEDEC JESD22-B111 Test Board http://works.bepress.com/pan/20 http://works.bepress.com/pan/20 Thu, 08 Jan 2009 14:11:32 PST Mobile and handheld electronic devices are prone to being dropped. This drop event may result in failure of solder joints inside these devices. The need for RoHS compliant boards coupled with the demand for reliable electronics has resulted in the development of the JEDEC Standard JESD22-B111 to standardize the method of drop testing surface mount electronic components. However, there has been little study on the effects of additional mass on the board and rigidity of the board on drop test reliability. This paper examines the drop impact dynamic responses of the JEDEC JESD22-B111 board. Of interest are the effects of an attached cable and rigidity of the board on the peak acceleration at different locations of the board. Fifteen 0.5 mm pitch CSPs were assembled on the board using SnAg3.0Cu0.5 lead free solder. The drop test was conducted using a Lansmont M23 TTSII Shock Test system. A half-sine shock impact pulse of 1500 G with 0.5 ms duration was applied to the drop table where the test vehicle was mounted. Two accelerometers were used to monitor the peak acceleration with one placed on the drop table and the other on the board at the component location. Statistical analysis showed that both the rigidity of the board and a cable attachment have an effect on the peak acceleration at individual component locations. Results show that the peak acceleration differs significantly at different component locations and the peak acceleration at some component locations are much higher than on the drop table. A cable attached to the board is shown to influence both peak acceleration and symmetry. A correlation between the peak acceleration and the number of drops until component failure was assessed.

]]> Michael Krist et al. Conference Proceedings Lead-free Solder Joint Reliability – State of the Art and Perspectives http://works.bepress.com/pan/19 http://works.bepress.com/pan/19 Thu, 08 Jan 2009 14:11:28 PST There is an increasing demand for replacing tin-lead (Sn/Pb) solders with lead-free solders in the electronics industry due to health and environmental concerns. The European Union recently passed a law to ban the use of lead in electronic products. The ban will go into effect in July of 2006. The Japanese electronics industry has worked to eliminate lead from consumer electronic products for several years. Although currently there are no specific regulations banning lead in electronics devices in the United States, many companies and consortiums are working on lead-free solder initiatives including Intel, Motorola, Agilent Technologies, General Electric, Boeing, NEMI and many others to avoid a commercial disadvantage. The solder joints reliability not only depends on the solder joint alloys, but also on the component and PCB metallizations. Reflow profile also has significant impact on lead-free solder joint performance because it influences wetting and microstructure of the solder joint. A majority of researchers use temperature cycling for accelerated reliability testing since the solder joint failure mainly comes from thermal stress due to CTE mismatch. A solder joint failure could be caused by crack initiation and growth or by macroscopic solder facture. There are conflicting views of the reliability comparison between lead-free solders and tin-lead solders. This paper first reviews lead-free solder alloys, lead-free component lead finishes, and lead-free PCB surface finishes. The issue of tin whiskers is also discussed. Next, lead-free solder joint testing methods are presented; finite element modeling of lead-free solder joint reliability is reviewed; and experimental data comparing lead-free and tin-lead solder joint reliability are summarized. Finally the paper gives perspectives of transitions to totally lead-free manufacturing.

]]> Jianbiao Pan et al. Articles