Floating point division and square root and the applications

Xiaojun Wang, Northeastern University
Miriam Leeser, Northeastern University

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Poster presented at the 2006 R3A Parallel Hardware Implementation for Fast Subsurface Detection Conference

Abstract

Division and square root are important operations in many high performance signal processing applications. We have implemented floating point division and square root based on Taylor series for the variable precision floating point library developed at the Reconfigurable Computing Laboratory at Northeastern. Our result shows that they are very well suited to FPGA implementations, and lead to a good tradeoff of area and latency. We implemented a floating-point K-means clustering algorithm and applied it to multispectral satellite images. The mean update is moved from host to FPGA hardware with the new fp_div module to reduce the communication between host and FPGA board and further accelerate the runtime. We are also working on QR factorization using both floating point divide and square root.