Article
Investigation of Tunneling Current in SiO2/HfO2 Gate Stacks for Flash Memory Applications
IEEE Transactions on Electron Devices
(2011)
Abstract
Despite theoretical predictions of significant performance improvement in Flash memory devices using tunnel-barrier-engineered (TBE) structures, there have been very few reports that demonstrate experimental verification. In this work, we have studied the role of factors such as high-k layer thickness and annealing recipe on the performance of SiO2/HfO2 gate stacks by electrical and physical characterization techniques. Results indicate that thick HfO2 is not suitable for use in SiO2/HfO2 stacks for tunnel barrier engineering applications. The performance of SiO2/HfO2 stacks improves with decreasing thickness of the HfO2 layer. Mild (10%) O2/N2 anneals do not significantly affect performance, although annealing above 600°C resulted in a slight decrease in the program current. Based on our observations, we propose a method to improve the program current in these structures and a simple hypothesis for the physical model for tunneling in SiO2/HfO2 stacks.
Keywords
- Charge traps,
- Fowler–Nordheim (F–N) tunneling,
- high-$k$ dielectric,
- tunnel barrier engineering
Disciplines
Publication Date
December, 2011
Citation Information
Bhaswar Chakrabarti, Heesoo Kang, Barry Brennan, Tae Joo Park, et al.. "Investigation of Tunneling Current in SiO2/HfO2 Gate Stacks for Flash Memory Applications" IEEE Transactions on Electron Devices Vol. 58 Iss. 12 (2011) Available at: http://works.bepress.com/kurtis_cantley/6/