Improving DSP Performance with a Small Amount of Field Programmable Logic

John Y. Oliver, University of California - Davis
Venkatesh Akella, University of California - Davis

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Copyright © 2003 Springer. The original publication is available at http://dx.doi.org/10.1007/b12007.

NOTE: At the time of publication, the author John Oliver was not yet affiliated with Cal Poly.

Abstract

We show a systematic methodology to create DSP + field-programmable logic hybrid architectures by viewing it as a hardware/software codesign problem. This enables an embedded processor architect to evaluate the trade-offs in the increase in die area due to the field programmable logic and the resultant improvement in performance or code size. We demonstrate our methodology with the implementation of a Viterbi decoder. A key result of the paper is that the addition of a field-programmable data alignment unit (FPDAU) between the register-file and the computational blocks provides 15%-22% improvement in the performance of a Viterbi decoder on the state-of-the-art TigerSHARC DSP. The area overhead of the FPDAU is small relative to the DSP die size and does not require any changes to the programming model or the instruction set architecture.