Articles
Life Cycle Aware Computing: Reusing Silicon Technology (with Rajeevan Amirtharajah, Venkatesh Akella, Roland Geyer, and Frederic T. Chong), Computer (2007)
Despite the high costs associated with processor manufacturing, the typical chip is used for only...
Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture (with Ravishankar Rao; Paul Sultana; Jedidiah Crandall; Erik Czernikowski; Leslie W. Jones, IV; Dean Copsey; Diana Keen; Venkatesh Akella; and Frederic T. Chong), Power-Aware Computer Systems (2005)
Embedded devices have hard performance targets and severe power and area constraints that depart significantly...
Improving DSP Performance with a Small Amount of Field Programmable Logic (with Venkatesh Akella), Field-Programmable Logic and Applications (2003)
We show a systematic methodology to create DSP + field-programmable logic hybrid architectures by viewing...
Conference Proceedings
Credit-based dynamic reliability management using online wearout detection (with Rajeevan Amirtharajah, Venkatesh Akella, and Frederic T. Chong), Proceedings of the 5th Conference on Computing Frontiers: Ischia, Italy (2008)
As circuit geometries continue to shrink, and supply voltages remain relatively constant, circuit wearout becomes...
Characterization of Error-Tolerant Applications when Protecting Control Data (with Darshan D. Thaker, Diana Franklin, Susmit Biswas, Derek Lockhart, Tzvetan Metodi, and Frederic T. Chong), Proceedings of the 2006 IEEE International Symposium on Workload Characterization: San Jose, CA (2006)
Soft errors have become a significant concern and recent studies have measured the "architectural vulnerability...
Tile size selection for low-power tile-based architectures (with Ravishankar Rao, Michael Brown, Jennifer Mankin, Diana Franklin, Frederic T. Chong, and Venkatesh Akella), Proceedings of the 3rd Conference on Computing Frontiers: Ischia, Italy (2006)
In this paper, we investigate the power implications of tile size selection for tile-based processors....
Efficient orchestration of sub-word parallelism in media processors (with Venkatesh Akella and Frederic T. Chong), Proceedings of the 16th Annual ACM Symposium on Parallelism in Algorithms and Architectures: Barcelona, Spain (2004)
Communication and multimedia applications with increased data rates and enhanced functionality continuously raise the bar...
Synchroscalar: a multiple clock domain, power-aware, tile-based embedded processor (with Ravishankar Rao; Paul Sultana; Jedidiah Crandall; Erik Czernikowski; Leslie W. Jones, IV; Diana Franklin; Venkatesh Akella; and Frederic T. Chong), Proceedings of the 31st Annual International Symposium on Computer Architecture: München, Germany (2004)
We present Synchroscalar, a tile-based architecture for embedded processing that is designed to provide the...