Article
Evaluating Conduction Loss of a Parallel IGBT-MOSFET Combination
Proceedings of the IEEE Industry Applications Conference/39th IAS Annual Meeting (2004, Seattle, WA)
Abstract
A variety of power devices are available to designers, each with specific advantages and limitations. For inverters, typically an IGBT combined with a p-i-n diode is used to obtain high current density. Recent developments in high-voltage MOSFETs support other alternatives. For example, a MOSFET can be paralleled with an IGBT to reduce losses at low currents, while the IGBT carries the load at high currents. The current work evaluates conduction losses in this configuration, showing applicability to generic inverters.
Meeting Name
IEEE Industry Applications Conference/39th IAS Annual Meeting (2004: Oct. 3-7, Seattle, WA)
Department(s)
Electrical and Computer Engineering
Sponsor(s)
Grainger CEME
Comments
The authors acknowledge the Grainger Center for Electric Machinery and Electromechanics for sponsoring the project.
Keywords and Phrases
- IGBT,
- MOSFET,
- Conduction Loss,
- Inverters,
- P-I-N Diode,
- Power Devices,
- Current Density,
- Electric Breakdown,
- Electric Inverters,
- Electric Losses,
- Electric Switches,
- Insulated Gate Bipolar Transistors,
- Thermal Load,
- Switching Loss,
- Thermal Response,
- MOSFET Devices
International Standard Book Number (ISBN)
780384865
Document Type
Article - Conference proceedings
Document Version
Final Version
File Type
text
Language(s)
English
Rights
© 2004 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
10-1-2004
Publication Date
01 Oct 2004
Disciplines
Citation Information
Jonathan W. Kimball and Patrick L. Chapman. "Evaluating Conduction Loss of a Parallel IGBT-MOSFET Combination" Proceedings of the IEEE Industry Applications Conference/39th IAS Annual Meeting (2004, Seattle, WA) Vol. 2 (2004) p. 1233 - 1237 ISSN: 0197-2618 Available at: http://works.bepress.com/jonathan-kimball/48/