A Low Distortion MOS Sampling Circuit
Article comments
Copyright 2002 IEEE. Reprinted from Proceedings of the IEEE International Symposium on Circuits and Systems 2002 (ISCAS 2002), Volume 5, pages V-585 - V-588.
Publisher URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isNumber=21767&page=9
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Abstract
This paper presents a sampling technique with reduced distortion for use in a sample-and-hold circuit for high resolution analog-to-digital converters and switched capacitor filters. The technique involves bootstrapping both the gate and the bulk terminal of the sampling switch to improve linearity. Circuit implementation and SPICE level simulation results are presented.
Suggested Citation
Sameer R. Sonkusale and Jan Van der Spiegel. "A Low Distortion MOS Sampling Circuit" Departmental Papers (ESE) (2002).
Available at: http://works.bepress.com/jan_vanderspiegel/6