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A CMOS Monolithic Implementation of a Nonliniear Interconnection Module for a Corticonic Network

Jie Yuan, University of Pennsylvania
Nabil H. Farhat, University of Pennsylvania
Jan Van der Spiegel, University of Pennsylvania

Article comments

Copyright 2006 IEEE. Reprinted from Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2006, May 2006, pages 2769-2772.

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Abstract

A nonlinear interconnection module for a corticonic network is designed and fabricated in a 0.6µm CMOS process. The module uses NMOS transistors in weak-inversion for nonlinearity. A calibration scheme is developed to compensate for the process and temperature variations of the circuit. The designed module has an area of 0.35 sq. mm2. It consumes 200mW of power, with 5V power supply. Simulation results show that the circuit is able to implement the target parametric coupling function accurately.

Suggested Citation

Jie Yuan, Nabil H. Farhat, and Jan Van der Spiegel. "A CMOS Monolithic Implementation of a Nonliniear Interconnection Module for a Corticonic Network" Departmental Papers (ESE) (2006).
Available at: http://works.bepress.com/jan_vanderspiegel/12